Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device including a through-electrode connecting conductive layers formed on one and the other surfaces of a semiconductor substrate, and a method for forming the through-electrode.
Related Art
As a technology for achieving additional high integration and high performance of semiconductor integrated circuits, there is a technology of stacking semiconductor chips with which a conductive layer provided on the main surface of the upper semiconductor chip is electrically connected to a conductive layer provided on the main surface of the lower semiconductor chip by a through-electrode formed in the upper semiconductor chip and in contact with the conductive layer of the upper semiconductor chip, and a bump between the through-electrode and the conductive layer of the lower semiconductor chip. Since the conductive layers are connected in the thickness direction of the semiconductor chip through the through-electrode and the bump, it is possible to greatly reduce the wiring length in comparison to outer wire connection and to transmit/receive a large number of signals by micro-fabrication, so that this technology is advantageous to achieve high performance.
The following technologies are known in the art, for a method of forming a through-electrode and the structure of the through-electrode.
Patent Document 1: JP-A-2009-124087
Patent Document 2: JP-A-2009-295851
Patent Document 3: JP-A-2008-53568
The technology described in Patent Document 1 includes forming a through-hole in a semiconductor substrate, plating copper in the through-hole, removing the copper on the surface of the semiconductor substrate by using a CMP method to complete a through-electrode, and then separately forming a bump by using a resist as a mask. The through-electrode is formed to have a plane shape or size in the view point of prevention of internal stress independently of the shape and size of the bump that is necessary for stacking the semiconductor chips. As a result, it is possible to completely individually adjust them. In generally, it is preferable to make the bump having a footprint larger than that of the through-electrode and thus an individual photolithography is generally used.
In the technologies described in Patent Documents 2 and 3, a conductive layer on an insulating film formed on the surface of a semiconductor chip and a through-electrode formed in the chip are connected through an opening formed in the insulating film, but the opening is smaller in diameter of the through-electrode, and the through-electrode and the bump are integrally formed. The through-electrode and the bump are formed by electroless plating, using a metal layer (conductive layer) exposed by the opening as a seed layer or using a seed layer covering the bottom of a through-hole. As a result, a plated layer is selectively formed in the through-hole without depositing a plated layer on the chip. Therefore, the number of manufacturing processes is less than the case of Patent Document 1. In addition, since the through-electrode and the bump are integrally formed, it is possible to accomplish low electric resistance.
In the technology described in Patent Document 1, the through-electrode and the bump are individually formed so that the processing of these components is long. Particularly, since it is necessary to remove the plated metal (copper) on the chip surface when forming the through-electrode, a CMP process that is expensive is necessary, which is economically unfavorable. Further, a barrier layer and a seed layer which have relatively large resistance are disposed between the through-electrode and the bump and the interface resistance is generated between the layers, such that it is difficult to sufficiently reduce electric resistance.
The through-electrode and the bump are formed by electroless plating after exposing the metal layer by the opening as a seed layer in the technology described in Patent Document 2, while after forming a seed layer on the bottom of the through-hole in contact with a contact plug connected to the metal layer through the insulating layer in the technology described in Patent Document 3. According to the electroless plating, the shape and size of them depend on the shape of the through-hole and cannot be individually adjusted. In Patent Documents 2 and 3, the diameters of the through-electrode and the bump are substantially the same, and accordingly, large internal stress is exerted in the wider through-electrode, such that a void may be generated by stress migration. Further, the speed forming a film is low in electroless plating, which cannot be considered as a preferable method for the productivity.